A traditional TDM-bus application consists of a data bus (DATA) (usually 8 bits), a data clock (CLK) and a frame synchronisation signal (FS). The time domain is divided into frames where each frame has a fixed duration (usually 125 μs). A frame synchronisation signal indicates the start of each frame and has a period as long as the frame duration. The frame synchronisation signal and the data clock comes from a synchronisation master source and are the timing master signals for all transmitters and receivers that are communicating via the TDM-bus. The frames are divided into a fixed number (N) of timeslots (TS) identified by local timeslot counters (CNT). The local timeslot counters are reset by the FS signal. In each TS data may be transmitted from a transmitter to a receiver using time division multiplexing (TDM).
The synchronisation Master regenerates the frame synchronisation signal from an incoming data stream containing a synchronisation pattern. The data clock is phase locked to the frame synchronisation signal to avoid bit glips during the transmission.
In most TDM-bus applications it is possible to configure more than one synchronisation source and more than one synchronisation master. If the active synchronisation source or the active synchronisation master fails, another will take over according to a priority list. If this happens it is important that the switch over from one data clock to another is done in a controlled way so that no bit faults appear. This is usually solved by phase locking all the synchronisation masters to the active synchronisation master, and at switch over, gradually phase lock the new synchronisation master data clock to the active synchronisation source.
The “H.110 Hardware Compatibility Specification: CT Bus” standard is an example of such a TDM-bus solution as described above.
The problems encountered with this conventional solution are:    1. In a system with a large number of TS within a frame, the data speed increases and the phase locking of the data clock becomes more complicated. Jitter, stability and delay problems introduced in the phase locked loop (PLL) limits the maximum data rate.    2. A controlled switch over from one data clock to another (i.e. if a synchronisation master fails), requires a slow PLL (low bandwidth loop filter) because the data clock must gradually switch over from one synchronisation source to another to avoid bit glips.    3. A slow PLL is complicated to implement in hardware (especially in integrated circuits), and jitter, stability and delay problems become greater the slower the PLL is.